efabless

Here are 11 public repositories matching this topic...

edabk-hust / edabk_brain_soc

A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated by ChatGPT-4 with advanced optimizations.

verilog soc snn efabless openlane chatgpt chatgpt4

Updated Feb 18, 2024
Verilog

mattvenn / wrapped_project_template

Star

Template project for the Zero to ASIC course group ASIC application

template google asic efabless sky130

Updated Jan 3, 2023
Verilog

saathi7 / Advanced-PD-using-OpenLANE-Sky130

Star

Creating this repo to document the learnings from the workshop Advanced Physical Design using OpenLANE/SKY130 conducted by VSD

vsd physical-design efabless openlane sky130

Updated Aug 7, 2022

rejunity / zero-to-asic-wrapped-parallax

Star

Tiny experimental ASIC design for efabless/OpenLane fab.

asic fpga verilog efabless openlane

Updated Nov 16, 2021
Verilog

mattvenn / zero_to_asic_mpw6

Star

MPW6 submission from the Zero to ASIC Course

asic verilog efabless sky130 mpw6

Updated Jun 22, 2022
Verilog

kisek / rvcore_chip2

Star

RISC-V Processor

asic efabless

Updated Dec 7, 2023
Verilog

Cognitive Direct-RF Sampling Transceiver: Massively pipelined SDR DSP baseband engine hardened on SkyWater 130nm for Efabless Caravel OpenMPW tapeout. 100-phase SystemVerilog RTL, OpenLane ASIC signoff, and 100% regression verified.