genus

This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

A general code generation tools for Go applications

Parameterized N×N output-stationary systolic array accelerator for INT8 neural network inference. Full RTL-to-GDS flow on ASAP7 7nm using Cadence Genus + Innovus. 667 MHz, 42.7 GOPS peak throughput, 0.33 mW/GOP. SystemVerilog RTL, synthesis, place-and-route and self-checking testbench included.

State of the art algorithms for computing the genus of a graph and visualizing the corresponding embedding. Python bindings, C code, and an interactive web app.

An application using Cadence IC Package

Genus is a generic hardware platform aimed at instrumentation in aerospace projects.

A library for computing Hecke matrices, eigenvectors, and eigenvalues for positive definite rational ternary quadratic forms.

CAN YOU EAT IT is a web application that allows users to identify fungi by location & season.

A complete ASIC design flow for a MNIST NPU. Features a quantized hardware-friendly architecture, SystemVerilog RTL implementation, and a verified backend-ready flow for logic synthesis and GDSII generation.

A high-performance, production-grade 64-bit RISC-V Multicore SoC ecosystem and industry-standard Cadence ASIC CAD flow (Genus/Innovus). Fully integrated 5-hart coherent core complex, TileLink interconnect, custom RoCC ML Systolic Array, PCIe, USB, HDMI, and silicon-proven IP blocks.

VHDL implementation of an "asynchronous" FIFO with 64 positions of 8-bit words. Features dual clock domains (wr_clk, rd_clk), asynchronous reset, status signals (empty, full, almost empty/full, error), testbench, synthesis scripts, and timing/power/area reports.

Standalone Cadence Genus & Innovus Flow

This work presents the design and implementation of high performance and low power 32-bit RISC-V processor 4-stage pipelined for non-load and 5-stage for load operations, also extending its capabilities as system on chip (SoC) design. RV32I with M extension designed for FPGA and ASIC

Python program to compute genera of surfaces into which simple 4-valent rigid vertex graphs can be embedded

Comparative VLSI design, layout, and simulation of an 8×8 6T SRAM cell array with embedded In-Memory Computing (IMC) capabilities across 180 nm, 90 nm, and 45 nm CMOS technology libraries in Cadence Virtuoso and cross checking functionality using VerilogHDL

On-Board Computer for aerospace systems

Attitude Determination and Control System for CubeSats

ASIC Physical Design implementation of a Secure Digital Door Lock using Verilog HDL, Cadence Genus, and Cadence Innovus.

Image Acquisition Component for aerospace systems

Communications and Data Handling for aerospace systems