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…6; fmha_sycl_check
…reads tails in place
…ached-KV for the expert)
…/up GEMMs for Gemma layers
…eads into the attention node
…chunks, LSE combine)
…ual, attention straight from the fused qkv
… in the o/down epilogues
…n act (no F32 intermediate)
…expert reads its K/V in place
…locks from the separate weights
…t scales applied by oneDNN
… opt-in (pi0.5); VLA_FQ_CHECK prints the F32 error
… and a softmax (prefix pack leaves the rows)
…e GEGLU in the gate/up kernel's epilogue
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Summary
π0.5 inference on the Intel Arc B390 iGPU (Core Ultra X7 358H, SYCL), for the SO101 11-task checkpoints in bf16, W8A8, W4A4 + o/down INT8 and W4A4. Denoise steps stay at 10 and
n_action_stepsis unchanged. Every shared-code change is opt-in, and only pi0.5 turns it on. Other models build the same graphs as before.--flash-attntests/fmha_sycl_check.src/sycl/vla_sycl_s4gemm.cpp) for the W4A4 sites of the prefix and the expert.VLA_FQ_NO_S4GEMM=1falls back to oneDNN.vla-server --warmup N(default 1) before binding.Latency
Intel PC, 2 × 224 views, 49-token prompt,
--flash-attn, 10 denoise steps, p50 of 10 runs.Vision drops from 77.5 to 24 ms.
Accuracy
VLA_FQ_CHECK=1: every FoldQuant node is byte-exact against the CPU reference.Test plan
VLA_FQ_CHECK=1per-node SYCL vs CPU check, 0 mismatchesvla-benchlatency table above